The present invention relates to integrated circuits (ICs), and more particularly to video processor ICs adapted to provide matching rates between input and output video frames.
Incoming data received by a video processor typically has a different resolution than the data supplied by the video processor, thereby requiring format conversion. For example, incoming data frames may have a resolution of 680*480 pixels per frame, whereas the output frames may require, for example, a frame resolution of 1280*1024 pixels. In conventional systems, to attempt to match the input and output frame rates, a combination of display clock frequency, display width and display height is determined by trial and error. Pixels might be added to or subtracted from either the horizontal width or vertical height of the output frame while the output clock frequency is varied in small steps. In general, a group of such settings is predetermined to handle different combinations of input and display frame rates that a system is expected to encounter. Accordingly, in conventional systems, the matching of the input/output frame rates is approximate and susceptible to inaccuracies such as input signal deviation from standard specifications or circuit component variations. Furthermore, such matching is not automatic.